ST STM32F732RET7

STM32F732RET7 Allgemeine Beschreibung

Core: Arm®32-bit Cortex®-M7 CPU with FPU, adaptive real-time accelerator (ART Accelerator) and L1-cache: 8 Kbytes of data cache and 8 Kbytes of instruction cache, allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1) and DSP instructions.MemoriesUp to 512 Kbytes of Flash memory with protection mechanisms (read and write protections, proprietary code readout protection (PCROP))528 bytes of OTP memorySRAM: 256 Kbytes (including 64 Kbytes of data TCM RAM for critical real-time data) + 16 Kbytes of instruction TCM RAM (for critical real-time routines) + 4 Kbytes of backup SRAM (available in the lowest power modes)Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memoriesDual mode Quad-SPIClock, reset and supply management1.7 V to 3.6 V application supply and I/OsPOR, PDR, PVD and BORDedicated USB power4-to-26 MHz crystal oscillatorInternal 16 MHz factory-trimmed RC (1% accuracy)32 kHz oscillator for RTC with calibrationInternal 32 kHz RC with calibrationLow-powerSleep, Stop and Standby modesVBATsupply for RTC, 32×32 bit backup registers + 4 Kbytes of backup SRAM3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode2×12-bit D/A convertersUp to 18 timers: up to thirteen 16-bit (1x low- power 16-bit timer available in Stop mode) and two 32-bit timers, each with up to 4 IC/OC/PWMs or pulse counter and quadrature (incremental) encoder inputs. All 15 timers running up to 216 MHz. 2x watchdogs, SysTick timerGeneral-purpose DMA: 16-stream DMA controller with FIFOs and burst supportDebug modeSWD and JTAG interfacesCortex®-M7 Trace Macrocell™Up to 140 I/O ports with interrupt capabilityUp to 136 fast I/Os up to 108 MHzUp to 138 5 V-tolerant I/OsUp to 21 communication interfacesUp to 3× I2C interfaces (SMBus/PMBus)Up to 4 USARTs/4 UARTs (27 Mbit/s, ISO7816 interface, LIN, IrDA, modem control)Up to 5 SPIs (up to 54 Mbit/s), 3 with muxed simplex I2Ss for audio class accuracy via internal audio PLL or external clock2 x SAIs (serial audio interface)1 x CAN (2.0B active)2 x SDMMCsAdvanced connectivityUSB 2.0 full-speed device/host/OTG controller with on-chip PHYUSB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and on-chip Hi-speed PHY or ULPI depending on the part numberAES: 128/256-bit key encryption hardware acceleratorTrue random number generatorCRC calculation unitRTC: subsecond accuracy, hardware calendar96-bit unique IDSTM32F7 System View DescriptionSTM32F7 System View Description1.0STM32F7 IBIS modelsSTM32F7 IBIS models3.0STM32F7 Boundary Scan Decription Language (BSDL) filesSTM32F7 Boundary Scan Decription Language (BSDL) files3.1

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