SAF-XC167CI-32F40F BB-A

SAF-XC167CI-32F40F BB-A Allgemeine Beschreibung

The SAF-XC167CI-32F40FBB-A microcontroller unit sets a new standard for embedded system design, providing developers with a powerful and feature-rich platform for their projects. With its high clock frequency, ample flash memory, and extensive peripheral integration, this MCU offers a comprehensive solution for a wide range of applications. Its flexibility, compatibility, and performance make it a top choice for engineers seeking a reliable and efficient microcontroller solution

Funktionen

• High Performance 16-bit CPU with 5-Stage Pipeline
• – 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
• – 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles
• – 1-Cycle Multiply-and-Accumulate (MAC) Instructions
• – Enhanced Boolean Bit Manipulation Facilities
• – Zero-Cycle Jump Execution
• – Additional Instructions to Support HLL and Operating Systems
• – Register-Based Design with Multiple Variable Register Banks
• – Fast Context Switching Support with Two Additional Local Register Banks
• – 16 Mbytes Total Linear Address Space for Code and Data
• – 1024 bytes On-Chip Special Function Register Area (C166 Family Compatible)
• 16-Priority-Level Interrupt System with 77 Sources, Sample-Rate down to 50 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
• Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or via Prescaler (factors 1:1 … 60:1)
• On-Chip Memory Modules
• – 2 Kbytes On-Chip Dual-Port RAM (DPRAM)
• – 4 Kbytes On-Chip Data SRAM (DSRAM)
• – 6 Kbytes On-Chip Program/Data SRAM (PSRAM)
• – 256 Kbytes On-Chip Program Memory (Flash Memory)
• On-Chip Peripheral Modules
• – 16-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and Conversion Time (down to 2.55 µs or 2.15 µs)
• – Two 16-Channel General Purpose Capture/Compare Units (32 Input/Output Pins)
• – Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6) (3/6 Capture/Compare Channels and 1 Compare Channel)
• – Multi-Functional General Purpose Timer Unit with 5 Timers
• – Two Synchronous/Asynchronous Serial Channels (USARTs)
• – Two High-Speed-Synchronous Serial Channels
• – On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects (Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality
• – IIC Bus Interface (10-bit addressing, 400 kbit/s) with 3 Channels (multiplexed)
• – On-Chip Real Time Clock, Driven by Dedicated Oscillator
• Idle, Sleep, and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 12 Mbytes External Address Space for Code and Data
• – Programmable External Bus Characteristics for Different Address Ranges
• – Multiplexed or Demultiplexed External Address/Data Buses
• – Selectable Address Bus Width
• – 16-bit or 8-bit Data Bus Width
• – Five Programmable Chip-Select Signals
• – Hold- and Hold-Acknowledge Bus Arbitration Support
• Up to 103 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
• On-Chip Bootstrap Loader
• Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Debug Support via JTAG Interface
• 144-Pin TQFP Package, 0.5 mm (19.7 mil) pitch

Spezifikationen