AT25DF021

AT25DF021 Allgemeine Beschreibung

DescriptionThe AT25DF021 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shad owed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25DF021, with its erase granularity as small as 4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storageEEPROM devices.Features• Single 2.3V - 3.6V or 2.7V - 3.6V Supply• Serial Peripheral Interface (SPI) Compatible– Supports SPI Modes 0 and 3• 66 MHz Maximum Operating Frequency– Clock-to-Output (tV) of 6 ns Maximum• Flexible, Optimized Erase Architecture for Code + Data Storage Applications– Uniform 4-Kbyte Block Erase– Uniform 32-Kbyte Block Erase– Uniform 64-Kbyte Block Erase– Full Chip Erase• Individual Sector Protection with Global Protect/Unprotect Feature– Four Sectors of 64 Kbytes Each• Hardware Controlled Locking of Protected Sectors via WP Pin• 128-Byte Programmable OTP Security Register• Flexible Programming– Byte/Page Program (1 to 256 Bytes)• Fast Program and Erase Times– 1.0 ms Typical Page Program (256 Bytes) Time– 50 ms Typical 4-Kbyte Block Erase Time– 250 ms Typical 32-Kbyte Block Erase Time– 450 ms Typical 64-Kbyte Block Erase Time• Automatic Checking and Reporting of Erase/Program Failures• JEDEC Standard Manufacturer and Device ID Read Methodology• Low Power Dissipation– 7 mA Active Read Current (Typical at 20 MHz)– 15 µA Deep Power-Down Current (Typical)• Endurance: 100,000 Program/Erase Cycles• Data Retention: 20 Years• Complies with Full Industrial Temperature Range• Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options– 8-lead SOIC (150-mil Wide)– 8-pad Ultra Thin DFN (5 x 6 x 0.6 mm)

Funktionen

• Single 2.3V - 3.6V or 2.7V - 3.6V Supply
• Serial Peripheral Interface (SPI) Compatible
• – Supports SPI Modes 0 and 3
• 66 MHz Maximum Operating Frequency
• – Clock-to-Output (tV) of 6 ns Maximum
• Flexible, Optimized Erase Architecture for Code + Data Storage Applications
• – Uniform 4-Kbyte Block Erase
• – Uniform 32-Kbyte Block Erase
• – Uniform 64-Kbyte Block Erase
• – Full Chip Erase
• Individual Sector Protection with Global Protect/Unprotect Feature
• – Four Sectors of 64 Kbytes Each
• Hardware Controlled Locking of Protected Sectors via WP Pin
• 128-Byte Programmable OTP Security Register
• Flexible Programming
• – Byte/Page Program (1 to 256 Bytes)
• Fast Program and Erase Times
• – 1.0 ms Typical Page Program (256 Bytes) Time
• – 50 ms Typical 4-Kbyte Block Erase Time
• – 250 ms Typical 32-Kbyte Block Erase Time
• – 450 ms Typical 64-Kbyte Block Erase Time
• Automatic Checking and Reporting of Erase/Program Failures
• JEDEC Standard Manufacturer and Device ID Read Methodology
• Low Power Dissipation
• – 7 mA Active Read Current (Typical at 20 MHz)
• – 15 µA Deep Power-Down Current (Typical)
• Endurance: 100,000 Program/Erase Cycles
• Data Retention: 20 Years
• Complies with Full Industrial Temperature Range
• Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
• – 8-lead SOIC (150-mil Wide)
• – 8-pad Ultra Thin DFN (5 x 6 x 0.6 mm)